1. Field of the Invention
The present invention generally relates to the manufacturing of metal-oxide-semiconductor field effect transistors (MOSFETs), and more particularly to fully depleted channel transistors fabricated in thin silicon films over a buried insulating layer with improved source drain characteristics, excellent electrostatic integrity and reduced statistical variability.
2. Prior Art
MOS transistors have long been troubled by the adverse effects of their underlying substrates, like parasitic capacitance and area-consuming isolation. In the earliest days of integrated circuit technology, the use of a thin film of silicon on a sapphire substrate was proposed as a solution to these problems. RCA Laboratories was an early proponent of this technology, as in Meyer, J. E.; Boleky, E. J.; “High performance, low power CMOS memories using silicon-on-sapphire technology,” Electron Devices Meeting, 1971 International, vol. 17, p. 44, 1971. The basic ideas of this technology have evolved over the years driven by improvements in materials technology, and as less exotic substrates became practical, this technology became known as silicon-on-insulator (SOI). In the earliest implementations, the silicon was simply relatively thin, i.e., less than 1 micron thick, substrate with a conventional level of doping and a depletion layer beneath the transistor's gate thinner than the silicon thickness resulting in ‘partially depleted’ SOI (PD SOI). The un-depleted doped region beneath the gate of a PD SOI transistor proved to have its own disadvantages, largely caused by its tendency to charge and discharge resulting in step changes in the drain current. These problems became known as a “kink” effect, and it was closely tied to impact ionization in the transistor's channel and electron/hole trapping in the un-depleted part of the silicon under the channel.
The next stage in SOI evolution was the use fully-depleted silicon film (FD SOI). This was achieved by making the silicon beneath the gate so thin that there would be no region where there could be mobile carriers. Some of the early work was done at HP Laboratories and reported as Colinge, J.-P.; “Hot-electron effects in Silicon-on-insulator n-channel MOSFET's,” Electron Devices, IEEE Transactions on, vol. 34, no. 10, pp. 2173-2177, October 1987. In this work, the silicon film is thinner by a factor of 10, only 100 nm thick.
The next step in fully depleted SOI technology has been prompted by the emergence of threshold voltage variations that are associated with the uncertainty of the number of discrete doping ions immediately beneath the gate. This uncertainty is similar to shot noise, because it is an irreducible, statistical uncertainty. For large devices, the counting uncertainty, roughly proportional to the square root of the total number of ions, was never a problem. However, in a world where devices have dimensions of the order of 30 nm, the total number of doping ions drops below 100, and the counting uncertainty is about 3%, rising to 10% for smaller devices. These deviations are devastating when billions of transistors are integrated into a single integrated circuit chip. The immediate solution required eliminating all doping from the silicon layer, placing all the responsibility for threshold control on the relative work functions of the gate material, now a metal, and the thickness of the silicon film. This has been done with both planar and FinFET transistor structures. A good review of this work may be found in Kuhn, K. J.; Giles, M. D.; Becher, D.; Kolar, P.; Kornfeld, A.; Kotlyar, R.; Ma, S. T.; Maheshwari, A.; Mudanai, S.; “Process Technology Variation,” Electron Devices, IEEE Transactions on, vol. 58, no. 8, pp. 2197-2208, August 2011.
Planar transistors at 32/28 nm CMOS technology generation made to have good electrostatic integrity and resistance to doping fluctuations have to employ extremely thin silicon layers, of the order of 7 nm or less, and they are fabricated over thin buried oxide layers, roughly 10 nm thick. This is discussed in detail in Maleville, C.; “Extending planar device roadmap beyond node 20 nm through ultra thin body technology,” VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on, pp. 1-4, 25-27 April 2011. Layers in the sub-10 nm thickness ranges present manufacturing challenges, and the very thin layers affect performance because the parasitic series resistance in sources and drains cuts down on the transistors' gain figures. The limited number of dopants, particularly in the access regions below the spacer, also introduce access resistance and on current variability, S. Markov, B. Cheng, A. Asenov, “Statistical variability in fully depleted SOI MOSFETs due to random dopant fluctuations in the Source and drain extensions,” IEEE Electron Dev. Let. Vol. 33, pp. 315-317 (March, 2012).
There have been a variety of publications that address the use of an undoped or lightly doped epitaxial channel region to mitigate the fluctuations associated with random doping variations. The publications include Takeuchi, K.; Tatsumi, T.; Furukawa, A.; “Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation,” Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International, pp. 841-844, 7-10 Dec. 1997; Asenov, A.; Saini, S.; “Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-μm MOSFET's with epitaxial and δ-doped channels,” Electron Devices, IEEE Transactions on, vol. 46, no. 8, pp. 1718-1724, August 1999; and Thompson; Scott E.; Thummalapally; Damodar R.; “Electronic Devices and Systems, and Methods for Making and Using the Same,” U.S. Patent Application 2011/0074498, Mar. 31, 2011. All these publications address the use of epitaxy in the channels of bulk transistors.
FIG. 1 shows a schematic representation of conventional, fully-depleted silicon on insulator transistor. This figure is prior art. The transistor in FIG. 1 is fabricated on a substrate 10, with a buried oxide 11 separating all components of the transistor from the underlying substrate 10. The active region 13 is intentionally undoped or doped at a low level that permits the active region to be totally free of carriers when there is no applied voltage difference between the gate 15 and 16 and the source, one of either region marked 19. This is made possible because a metal gate 15 has been chosen to have a work function which establishes the appropriate electrostatic potentials within the silicon channel region 13. The gate region 16 is a robust material like polycrystalline silicon that permits fabrication of further structures like inter-layer dielectrics and contacts. Normally in the fabrication of such a transistor, there is a protective oxide 17 which is removed and replaced by a thin, high dielectric constant stack identified as 14. On each side of the gate structure comprising elements 14, 15 and 16, there is a spacer 18. Typically, this spacer is a robust dielectric like silicon nitride that has been etched anisotropically to leave walls of finite thickness on each side of the gate structure.
Within the current FDSOI practice there remain problems associated with low and variable access conductance beneath the gate spacers and with thickness control of the active layer. These problems are addressed by the structure and methods described below.